Building a Hexadecimal Display using AHDL

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Here is the code for a Binary-to-Hexadecimal Decoder for seven-segment displays implemented on Altera’s Hardware Decription Language (AHDL), the language for building logic blocks inside Altera’s Quartus II.

An optional invert input (named N) is provided to invert the decoder outputs, which is often necessary if you plan to emulate your device using a FPGA and it happens to have its output display with inverted logic activation. This code also serves as a example on how to program a logic function by using its truth table directly in AHDL.

To use this code in your Quartus II project, open up your project, then click

“File -> New”,

choose “AHDL File”, copy and paste this code and then click

“File -> Create / Update -> Create Symbol Files for Current File”

to create its symbol file. After that, you may add the decoder to your schematics as if you were adding a common component to your circuit using the Symbol Tool dialog. The symbol should be located under the Project library.

For more information about using AHDL and Quartus, you may read this guide, Using AHDL in the Quartus II Software. There is a lot of other resources available online teaching how to use Quartus II out there. Some of them can be found on the following links:



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specific device designations, and all other words that are identified
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Altera Corporation in the U.S. and
other countries. Other linked content from here are copyrighted from its respective owners. The AHDL code provided above belongs to the
public domain.

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